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[/] [ha1588/] [trunk/] [rtl/] [reg/] [reg.v] - Rev 37

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37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4458d 12h /ha1588/trunk/rtl/reg/reg.v
34 Added LGPL file header to all copyrighted files. edn_walter 4460d 09h /ha1588/trunk/rtl/reg/reg.v
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4460d 10h /ha1588/trunk/rtl/reg/reg.v
31 Added hand-shaking for the TSU data reading. edn_walter 4461d 06h /ha1588/trunk/rtl/reg/reg.v
27 Added more bits to the TSU queue information, of which timestamp value is enlarged from 4s to 64s. edn_walter 4461d 12h /ha1588/trunk/rtl/reg/reg.v
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4464d 08h /ha1588/trunk/rtl/reg/reg.v
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4465d 02h /ha1588/trunk/rtl/reg/reg.v
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4466d 02h /ha1588/trunk/rtl/reg/reg.v
18 Added QuartusII Place and Route project for top level ha1588.v edn_walter 4470d 07h /ha1588/trunk/rtl/reg/reg.v
17 Updated reg.v content. edn_walter 4471d 00h /ha1588/trunk/rtl/reg/reg.v
16 Try to add sth. edn_walter 4474d 17h /ha1588/trunk/rtl/reg/reg.v
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4477d 02h /ha1588/trunk/rtl/reg/reg.v

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