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[/] [ha1588/] [trunk/] [rtl/] [rtc/] [rtc.v] - Rev 69

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69 Fixed the negative period adjustment bug. ash_riple 4158d 08h /ha1588/trunk/rtl/rtc/rtc.v
58 Added output rtc_time_one_pps for clock accuracy measurement. 1PPS output is leading edge aligned with the PTP time output on boundary of 1s. edn_walter 4443d 07h /ha1588/trunk/rtl/rtc/rtc.v
45 1. optimized area, by removing unused registers.
2. optimized timing, by removing latches.		 edn_walter 4454d 21h /ha1588/trunk/rtl/rtc/rtc.v
41 Added pre-adder to the accumulator to cut down critical timing path. edn_walter 4456d 05h /ha1588/trunk/rtl/rtc/rtc.v
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4456d 08h /ha1588/trunk/rtl/rtc/rtc.v
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4457d 06h /ha1588/trunk/rtl/rtc/rtc.v
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4457d 09h /ha1588/trunk/rtl/rtc/rtc.v
34 Added LGPL file header to all copyrighted files. edn_walter 4459d 06h /ha1588/trunk/rtl/rtc/rtc.v
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4459d 10h /ha1588/trunk/rtl/rtc/rtc.v
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4464d 03h /ha1588/trunk/rtl/rtc/rtc.v
19 Added pipeline registers to Real Time Clock module to improve timing. edn_walter 4469d 04h /ha1588/trunk/rtl/rtc/rtc.v
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4475d 23h /ha1588/trunk/rtl/rtc/rtc.v
3 Added function block RTC and its unit test. ash_riple 4493d 22h /ha1588/trunk/rtl/rtc/rtc_timer.v

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