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[/] [ha1588/] [trunk/] [sim/] [top/] [ptp_drv_bfm] - Rev 46

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46 Added operation details to the memory map doc. Memory map should be interpreted with help of ptp_drv_bfm.c. edn_walter 4595d 02h /ha1588/trunk/sim/top/ptp_drv_bfm
44 Updated TSU testbench. edn_walter 4595d 20h /ha1588/trunk/sim/top/ptp_drv_bfm
43 Added software configurable PTP message id mask for TSU parser. edn_walter 4596d 18h /ha1588/trunk/sim/top/ptp_drv_bfm
39 1. Added memory map and feature description.
2. Separated TX RX TSU register addresses.		 edn_walter 4597d 05h /ha1588/trunk/sim/top/ptp_drv_bfm
38 1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c.
2. Added adj_done signal for CPU polling.
3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.		 edn_walter 4598d 03h /ha1588/trunk/sim/top/ptp_drv_bfm
37 Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit edn_walter 4598d 06h /ha1588/trunk/sim/top/ptp_drv_bfm
34 Added LGPL file header to all copyrighted files. edn_walter 4600d 03h /ha1588/trunk/sim/top/ptp_drv_bfm
33 Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules. edn_walter 4600d 04h /ha1588/trunk/sim/top/ptp_drv_bfm
31 Added hand-shaking for the TSU data reading. edn_walter 4601d 00h /ha1588/trunk/sim/top/ptp_drv_bfm
26 Updated test case. edn_walter 4603d 01h /ha1588/trunk/sim/top/ptp_drv_bfm
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4604d 02h /ha1588/trunk/sim/top/ptp_drv_bfm
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4604d 20h /ha1588/trunk/sim/top/ptp_drv_bfm
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4605d 00h /ha1588/trunk/sim/top/ptp_drv_bfm
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4605d 20h /ha1588/trunk/sim/top/ptp_drv_bfm

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