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[/] [ha1588/] [trunk/] [sim/] [top] - Rev 31

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31 Added hand-shaking for the TSU data reading. edn_walter 4501d 13h /ha1588/trunk/sim/top
29 Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz. edn_walter 4501d 13h /ha1588/trunk/sim/top
26 Updated test case. edn_walter 4503d 14h /ha1588/trunk/sim/top
24 Added test cases for top-level testbench to cover both RTC and TSU. edn_walter 4504d 15h /ha1588/trunk/sim/top
23 Added CDC hand-shaking for RTC time reading operation. edn_walter 4505d 09h /ha1588/trunk/sim/top
22 RTC reset will clear ACC counter, but not clear ACC counter incremental. edn_walter 4505d 13h /ha1588/trunk/sim/top
21 Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application. edn_walter 4506d 09h /ha1588/trunk/sim/top
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.
edn_walter 4517d 09h /ha1588/trunk/sim/top

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