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[/] [ha1588/] [trunk/] [sim/] [tsu/] [tsu_queue_tb.v] - Rev 36

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36 TSU testbench is now self-checking. Test result is reported at end of simulation. edn_walter 4456d 16h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
35 Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets. edn_walter 4457d 15h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
34 Added LGPL file header to all copyrighted files. edn_walter 4457d 18h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
32 Added PTP standard time format output to the top module. Can be connected to external modules. edn_walter 4457d 21h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
30 Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit edn_walter 4458d 15h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
15 Renamed module name for tsu and rtc.
Added folder for reg and top.
Added folder for sopc, preparing for Altera SOPC Builder customized component.		 edn_walter 4474d 11h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
13 Added test case support for single VLAN and double VLAN L2/L4 PTP frames. edn_walter 4477d 11h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
12 Added parser support for vlan tagged frames. edn_walter 4478d 09h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
9 Timestamp format in the queue = seqId_16bit + msgId_4bit + timeStamp1s_2bit + timeStamp1ns_30bit edn_walter 4481d 10h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
8 Timestamp format in the queue = seqId_16bit + msgId_2bit + timeStamp_30bit edn_walter 4481d 17h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
7 Reduced the timestamp length from 80b to 30b to save memory, since the software could be fast enough to handle timestamp rollover events per 1s. Enlarged the fifo depth to 15, to accomodate 10 ptp sync messages per 1s. edn_walter 4481d 18h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
5 Added dcfifo to store ptp time stamps. ash_riple 4484d 09h /ha1588/trunk/sim/tsu/tsu_queue_tb.v
4 Added source code and unit test for TSU. ash_riple 4485d 10h /ha1588/trunk/sim/tsu/tsu_queue_tb.v

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