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[/] [heap_sorter/] [trunk/] [standard_version/] [src] - Rev 5

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5 Added new high-speed version capable to work at higher speed, but using 4
clk cycles per data word.
wzab 2273d 12h /heap_sorter/trunk/standard_version/src
4 Added file implementing dual port common clock RAM inferrable in synthesis. wzab 3985d 09h /src
3 Eliminated synthesis of latches for a few signals wzab 3985d 10h /src
2 Initial commit of version previously hosted at http://www.ise.pw.edu.pl/~wzab/fpga_heapsort wzab 4246d 16h /src

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