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[/] [heap_sorter] - Rev 6

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6 High-speed version with comparator moved from a function to the
separate VHDL component (with 1 clock period latency).
It allows better utilization of the platform-specific features.
wzab 2314d 08h /heap_sorter
5 Added new high-speed version capable to work at higher speed, but using 4
clk cycles per data word.
wzab 2314d 22h /heap_sorter
4 Added file implementing dual port common clock RAM inferrable in synthesis. wzab 4026d 19h /heap_sorter
3 Eliminated synthesis of latches for a few signals wzab 4026d 20h /heap_sorter
2 Initial commit of version previously hosted at http://www.ise.pw.edu.pl/~wzab/fpga_heapsort wzab 4288d 03h /heap_sorter
1 The project and the structure was created root 4289d 19h /heap_sorter

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