URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_2/] [rtl/] [verilog/] [i2c_master_top.v] - Rev 68

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5579d 13h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
41	This commit was manufactured by cvs2svn to create tag 'asyst_2'.		7596d 01h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7596d 01h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
33	Fixed a bug in the Command Register declaration.	rherveille	7830d 19h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
30	Small code simplifications	rherveille	7844d 20h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
29	Core is now a Multimaster I2C controller	rherveille	7844d 21h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
27	Cleaned up code	rherveille	7870d 13h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8256d 01h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8261d 00h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
13	Fixed some synthesis warnings.	rherveille	8272d 04h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
11	Changed RST_LVL define to parameter.	rherveille	8281d 03h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v
10	Created new directory structure. Added Verilog version.	rherveille	8302d 23h	/i2c/tags/asyst_2/rtl/verilog/i2c_master_top.v