URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3/] [rtl/] [verilog/] [i2c_master_bit_ctrl.v] - Rev 30

Rev	Log message	Author	Age	Path
30	Small code simplifications	rherveille	7832d 19h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v
29	Core is now a Multimaster I2C controller	rherveille	7832d 20h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v
27	Cleaned up code	rherveille	7858d 13h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7889d 17h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8027d 03h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8248d 23h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v
10	Created new directory structure. Added Verilog version.	rherveille	8290d 23h	/i2c/tags/asyst_3/rtl/verilog/i2c_master_bit_ctrl.v