URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [asyst_3] - Rev 15

Rev	Log message	Author	Age	Path
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8311d 06h	/i2c/tags/asyst_3
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8311d 06h	/i2c/tags/asyst_3
13	Fixed some synthesis warnings.	rherveille	8322d 11h	/i2c/tags/asyst_3
12	no message	rherveille	8328d 02h	/i2c/tags/asyst_3
11	Changed RST_LVL define to parameter.	rherveille	8331d 10h	/i2c/tags/asyst_3
10	Created new directory structure. Added Verilog version.	rherveille	8353d 06h	/i2c/tags/asyst_3
9	Created directory structure (documentation, vhdl, verilog)	rherveille	8423d 01h	/i2c/tags/asyst_3
8	Created directory structure (documentation, vhdl, verilog)	rherveille	8423d 01h	/i2c/tags/asyst_3
7	added some remarks, fixed some sensitivity lists	rherveille	8492d 04h	/i2c/tags/asyst_3
6	fixed typo txt -> txr	rherveille	8496d 08h	/i2c/tags/asyst_3
5	fixed an incomplete sensitivity list on assign_dato process	rherveille	8503d 06h	/i2c/tags/asyst_3
4	WISHBONE I2C Master Core: initial release	rherveille	8555d 09h	/i2c/tags/asyst_3
2	initial release	rherveille	8617d 08h	/i2c/tags/asyst_3
1	Standard project directories initialized by cvs2svn.		8617d 08h	/i2c/tags/asyst_3