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[/] [i2c/] [tags/] [asyst_3] - Rev 19

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Rev Log message Author Age Path
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8179d 09h /i2c/tags/asyst_3
18 no message rherveille 8206d 04h /i2c/tags/asyst_3
17 C-include file.
Initial release		 rherveille 8294d 09h /i2c/tags/asyst_3
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8306d 08h /i2c/tags/asyst_3
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8311d 07h /i2c/tags/asyst_3
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8311d 07h /i2c/tags/asyst_3
13 Fixed some synthesis warnings. rherveille 8322d 11h /i2c/tags/asyst_3
12 no message rherveille 8328d 03h /i2c/tags/asyst_3
11 Changed RST_LVL define to parameter. rherveille 8331d 10h /i2c/tags/asyst_3
10 Created new directory structure.
Added Verilog version.		 rherveille 8353d 07h /i2c/tags/asyst_3
9 Created directory structure (documentation, vhdl, verilog) rherveille 8423d 02h /i2c/tags/asyst_3
8 Created directory structure (documentation, vhdl, verilog) rherveille 8423d 02h /i2c/tags/asyst_3
7 added some remarks, fixed some sensitivity lists rherveille 8492d 04h /i2c/tags/asyst_3
6 fixed typo txt -> txr rherveille 8496d 08h /i2c/tags/asyst_3
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8503d 06h /i2c/tags/asyst_3
4 WISHBONE I2C Master Core: initial release rherveille 8555d 09h /i2c/tags/asyst_3
2 initial release rherveille 8617d 09h /i2c/tags/asyst_3
1 Standard project directories initialized by cvs2svn. 8617d 09h /i2c/tags/asyst_3

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