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[/] [i2c/] [tags/] [rel_1/] [rtl/] [verilog/] [i2c_master_bit_ctrl.v] - Rev 68

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Rev Log message Author Age Path
68 New directory structure. root 5581d 16h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7588d 06h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7621d 07h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
36 Fixed cmd_ack generation item (no bug). rherveille 7773d 00h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7806d 14h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
30 Small code simplifications rherveille 7846d 22h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
29 Core is now a Multimaster I2C controller rherveille 7846d 23h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
27 Cleaned up code rherveille 7872d 16h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7903d 20h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8041d 07h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8263d 03h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v
10 Created new directory structure.
Added Verilog version.		 rherveille 8305d 02h /i2c/tags/rel_1/rtl/verilog/i2c_master_bit_ctrl.v

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