URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [tags/] [rel_1/] [rtl] - Rev 28

Rev	Log message	Author	Age	Path
28	* empty log message *	rherveille	7946d 19h	/i2c/tags/rel_1/rtl
27	Cleaned up code	rherveille	7946d 19h	/i2c/tags/rel_1/rtl
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7977d 23h	/i2c/tags/rel_1/rtl
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8115d 10h	/i2c/tags/rel_1/rtl
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8332d 06h	/i2c/tags/rel_1/rtl
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8337d 05h	/i2c/tags/rel_1/rtl
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8337d 05h	/i2c/tags/rel_1/rtl
13	Fixed some synthesis warnings.	rherveille	8348d 09h	/i2c/tags/rel_1/rtl
11	Changed RST_LVL define to parameter.	rherveille	8357d 08h	/i2c/tags/rel_1/rtl
10	Created new directory structure. Added Verilog version.	rherveille	8379d 05h	/i2c/tags/rel_1/rtl