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[/] [i2c/] [tags/] [rel_1] - Rev 23

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Rev Log message Author Age Path
23 *** empty log message *** rherveille 8018d 00h /i2c/tags/rel_1
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8028d 05h /i2c/tags/rel_1
21 no message rherveille 8114d 06h /i2c/tags/rel_1
20 Added Appendix A rherveille 8114d 06h /i2c/tags/rel_1
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8118d 02h /i2c/tags/rel_1
18 no message rherveille 8144d 22h /i2c/tags/rel_1
17 C-include file.
Initial release		 rherveille 8233d 03h /i2c/tags/rel_1
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8245d 02h /i2c/tags/rel_1
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8250d 01h /i2c/tags/rel_1
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8250d 01h /i2c/tags/rel_1
13 Fixed some synthesis warnings. rherveille 8261d 05h /i2c/tags/rel_1
12 no message rherveille 8266d 20h /i2c/tags/rel_1
11 Changed RST_LVL define to parameter. rherveille 8270d 04h /i2c/tags/rel_1
10 Created new directory structure.
Added Verilog version.		 rherveille 8292d 00h /i2c/tags/rel_1
9 Created directory structure (documentation, vhdl, verilog) rherveille 8361d 19h /i2c/tags/rel_1
8 Created directory structure (documentation, vhdl, verilog) rherveille 8361d 20h /i2c/tags/rel_1
7 added some remarks, fixed some sensitivity lists rherveille 8430d 22h /i2c/tags/rel_1
6 fixed typo txt -> txr rherveille 8435d 02h /i2c/tags/rel_1
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8442d 00h /i2c/tags/rel_1
4 WISHBONE I2C Master Core: initial release rherveille 8494d 03h /i2c/tags/rel_1

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