URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Rev 68

Rev	Log message	Author	Age	Path
68	New directory structure.	root	5790d 16h	/i2c/trunk/bench/verilog/tst_bench_top.v
58	fixed (n)ack generation	rherveille	6708d 05h	/i2c/trunk/bench/verilog/tst_bench_top.v
54	Fixed scl, sda delay.	rherveille	7262d 05h	/i2c/trunk/bench/verilog/tst_bench_top.v
50	* empty log message *	rherveille	7626d 23h	/i2c/trunk/bench/verilog/tst_bench_top.v
49	Added testbench	rherveille	7626d 23h	/i2c/trunk/bench/verilog/tst_bench_top.v
45	Added slave address configurability	rherveille	7712d 03h	/i2c/trunk/bench/verilog/tst_bench_top.v
25	Added timing tests to i2c_model. Updated testbench.	rherveille	8112d 20h	/i2c/trunk/bench/verilog/tst_bench_top.v
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8340d 04h	/i2c/trunk/bench/verilog/tst_bench_top.v
10	Created new directory structure. Added Verilog version.	rherveille	8514d 02h	/i2c/trunk/bench/verilog/tst_bench_top.v