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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_bit_ctrl.v] - Rev 57

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Rev Log message Author Age Path
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6490d 13h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7340d 11h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7612d 15h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
36 Fixed cmd_ack generation item (no bug). rherveille 7764d 08h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7797d 22h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
30 Small code simplifications rherveille 7838d 06h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
29 Core is now a Multimaster I2C controller rherveille 7838d 07h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
27 Cleaned up code rherveille 7864d 00h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7895d 04h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8032d 14h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8254d 10h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
10 Created new directory structure.
Added Verilog version.		 rherveille 8296d 10h /i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v

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