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[/] [i2c/] [trunk/] [rtl/] [verilog] - Rev 52

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Rev Log message Author Age Path
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7345d 21h /i2c/trunk/rtl/verilog
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7424d 21h /i2c/trunk/rtl/verilog
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7594d 22h /i2c/trunk/rtl/verilog
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7618d 02h /i2c/trunk/rtl/verilog
36 Fixed cmd_ack generation item (no bug). rherveille 7769d 18h /i2c/trunk/rtl/verilog
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7803d 08h /i2c/trunk/rtl/verilog
33 Fixed a bug in the Command Register declaration. rherveille 7829d 16h /i2c/trunk/rtl/verilog
30 Small code simplifications rherveille 7843d 16h /i2c/trunk/rtl/verilog
29 Core is now a Multimaster I2C controller rherveille 7843d 18h /i2c/trunk/rtl/verilog
27 Cleaned up code rherveille 7869d 10h /i2c/trunk/rtl/verilog
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7900d 14h /i2c/trunk/rtl/verilog
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8038d 01h /i2c/trunk/rtl/verilog
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8254d 22h /i2c/trunk/rtl/verilog
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8259d 21h /i2c/trunk/rtl/verilog
13 Fixed some synthesis warnings. rherveille 8271d 01h /i2c/trunk/rtl/verilog
11 Changed RST_LVL define to parameter. rherveille 8280d 00h /i2c/trunk/rtl/verilog
10 Created new directory structure.
Added Verilog version.		 rherveille 8301d 20h /i2c/trunk/rtl/verilog

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