URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl] - Rev 33

Rev	Log message	Author	Age	Path
33	Fixed a bug in the Command Register declaration.	rherveille	7829d 19h	/i2c/trunk/rtl
31	Core is now a Multimaster I2C controller.	rherveille	7843d 20h	/i2c/trunk/rtl
30	Small code simplifications	rherveille	7843d 20h	/i2c/trunk/rtl
29	Core is now a Multimaster I2C controller	rherveille	7843d 21h	/i2c/trunk/rtl
28	* empty log message *	rherveille	7869d 13h	/i2c/trunk/rtl
27	Cleaned up code	rherveille	7869d 13h	/i2c/trunk/rtl
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7900d 17h	/i2c/trunk/rtl
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8038d 04h	/i2c/trunk/rtl
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8255d 01h	/i2c/trunk/rtl
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8260d 00h	/i2c/trunk/rtl
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8260d 00h	/i2c/trunk/rtl
13	Fixed some synthesis warnings.	rherveille	8271d 04h	/i2c/trunk/rtl
11	Changed RST_LVL define to parameter.	rherveille	8280d 03h	/i2c/trunk/rtl
10	Created new directory structure. Added Verilog version.	rherveille	8301d 23h	/i2c/trunk/rtl