OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [src/] [opcodes/] [opcodes.s] - Rev 203

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
203 Opcode test program prepared to test interrupts
(by using special simulated hardware in the test bench)
More changes to come, this is just the first commit of many		 ja_rd 4736d 10h /ion/trunk/src/opcodes/opcodes.s
165 Added (very early draft, very incomplete) reserved opcode trap handler.
Updated opcode tester to test some emulated mips32 opcodes using the trap handler.		 ja_rd 4787d 16h /ion/trunk/src/opcodes/opcodes.s
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4791d 12h /ion/trunk/src/opcodes/opcodes.s
150 Bug fix: added missing nop in vacant branch delay slot ja_rd 4792d 10h /ion/trunk/src/opcodes/opcodes.s
148 Added optional cache support to 'opcodes' test.
Updated simulation length accordingly.		 ja_rd 4794d 01h /ion/trunk/src/opcodes/opcodes.s
110 Updated 'opcodes' code sample:
- Longer simulated time for compatibility to new cache		 ja_rd 4854d 15h /ion/trunk/src/opcodes/opcodes.s
90 Added 'Adventure' demo to be run from the DE-1 FLASH ja_rd 4898d 12h /ion/trunk/src/opcodes/opcodes.s
66 Code samples:
Updated all code samples to use TB2 template and new memory map		 ja_rd 4909d 02h /ion/trunk/src/opcodes/opcodes.s
38 Minor changes in header comments ja_rd 4915d 11h /ion/trunk/src/opcodes/opcodes.s
29 opcode test updated:
supports CP0 cause register and traps in delay slots
tests that traps abort next instruction in all cases		 ja_rd 4917d 09h /ion/trunk/src/opcodes/opcodes.s
25 opcode test:
HO and LO registers tested along with mul/div and not separately		 ja_rd 4917d 14h /ion/trunk/src/opcodes/opcodes.s
14 Opcode test now has mul/div tests enabled by default ja_rd 4919d 01h /ion/trunk/src/opcodes/opcodes.s
9 Trap handling now works as in the MIPS specs:
EPC points to victim instruction (break/syscall)
Opcode test modified accordingly		 ja_rd 4920d 02h /ion/trunk/src/opcodes/opcodes.s
4 New test for BREAK: abortion of load and jump
Added comment to readme file		 ja_rd 4920d 05h /ion/trunk/src/opcodes/opcodes.s
2 First commit (includes 'hello' demo) ja_rd 4920d 14h /ion/trunk/src/opcodes/opcodes.s

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.