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[/] [ion/] [trunk/] [vhdl/] [SoC/] [mips_soc.vhdl] - Rev 223

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Rev Log message Author Age Path
223 MCU entity renamed to SoC, moved to separate SoC directory ja_rd 4399d 10h /ion/trunk/vhdl/SoC/mips_soc.vhdl
200 CPU interrupt input changed to 8-bit vector
Other modules changed accordingly
Interrupts still missing; this is just preparing the interface		 ja_rd 4724d 03h /ion/trunk/vhdl/demo/mips_mpu.vhdl
193 Major test bench reorganization:
1.- TB now uses same object code as synthesizable demo.
2.- TB now simulates full MPU system.
3.- Console logging moved to TB package.
4.- Code sample makefiles and modelsim script updated accordingly.		 ja_rd 4725d 18h /ion/trunk/vhdl/demo/mips_mpu.vhdl
191 Separated object code stuff from mcu entity
Object code related stuff now lives in separate file
Makefiles for code samples updated accordingly
Old mcu template deprecated but still in place		 ja_rd 4730d 04h /ion/trunk/vhdl/demo/mips_mpu.vhdl
188 updated hello demo mpu file ja_rd 4738d 21h /ion/trunk/vhdl/demo/mips_mpu.vhdl
138 updated simulation & synthesis pre-generated entities
('hello' code sample)		 ja_rd 4784d 03h /ion/trunk/vhdl/demo/mips_mpu.vhdl
129 updated pregenerated demo ('hello') ja_rd 4787d 01h /ion/trunk/vhdl/demo/mips_mpu.vhdl
119 Updated pre-generated simulation and synthesis demos ja_rd 4842d 03h /ion/trunk/vhdl/demo/mips_mpu.vhdl
98 CPU rd and wr data address buses unified ja_rd 4875d 08h /ion/trunk/vhdl/demo/mips_mpu.vhdl
94 Pregenerated demo 'hello' files updated ja_rd 4886d 04h /ion/trunk/vhdl/demo/mips_mpu.vhdl
76 Adapted pregenerated vhdl files to latest changes ja_rd 4896d 02h /ion/trunk/vhdl/demo/mips_mpu.vhdl
68 Updated pre-generated vhdl files ja_rd 4896d 18h /ion/trunk/vhdl/demo/mips_mpu.vhdl
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 4898d 08h /ion/trunk/vhdl/demo/mips_mpu.vhdl
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit		 ja_rd 4898d 21h /ion/trunk/vhdl/demo/mips_mpu.vhdl
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache		 ja_rd 4899d 00h /ion/trunk/vhdl/demo/mips_mpu.vhdl
40 pre-generated 'hello' demo updated ja_rd 4903d 03h /ion/trunk/vhdl/demo/mips_mpu.vhdl
2 First commit (includes 'hello' demo) ja_rd 4908d 07h /ion/trunk/vhdl/demo/mips_mpu.vhdl

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