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[/] [ion/] [trunk/] [vhdl/] [mips_cache.vhdl] - Rev 242

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Rev Log message Author Age Path
242 BUG FIX:
The CPU was sometimes fetching a spurious opcode in the 1st cycle after a reset.
The cache now has a 'cache_ready' output which the CPU uses to know when NOT to update its IR.		 ja_rd 4215d 18h /ion/trunk/vhdl/mips_cache.vhdl
235 Fixed comments in cache module ja_rd 4216d 19h /ion/trunk/vhdl/mips_cache.vhdl
212 BUG FIX: sequences of back-to-back I/O reads or writes didn't work.
The stall conditions were wrong for those cases.
Minor cleanup of the comments		 ja_rd 4374d 22h /ion/trunk/vhdl/mips_cache.vhdl
201 Minor fixes to code comments ja_rd 4688d 17h /ion/trunk/vhdl/mips_cache.vhdl
162 Fixed stupid mistake in headers (date of project) ja_rd 4740d 15h /ion/trunk/vhdl/mips_cache.vhdl
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)		 ja_rd 4740d 15h /ion/trunk/vhdl/mips_cache.vhdl
151 BUG FIX: major bugs fixed in cache module
1.- sram address was wrong (leftover from previous version)
2.- writes to unmapped areas were blocking the cache
3.- Sequence SW,LW produced a RAW data hazard in some cases		 ja_rd 4743d 20h /ion/trunk/vhdl/mips_cache.vhdl
145 MAJOR UPDATE: first version of D-Cache ja_rd 4746d 10h /ion/trunk/vhdl/mips_cache.vhdl
141 BUG FIX in cache: cpu stall logic was missing key case
2nd SW in a (cached) row was not being stalled		 ja_rd 4748d 00h /ion/trunk/vhdl/mips_cache.vhdl
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.		 ja_rd 4748d 17h /ion/trunk/vhdl/mips_cache.vhdl
114 ADDED: 1st version of real cache ja_rd 4806d 21h /ion/trunk/vhdl/mips_cache.vhdl

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