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[/] [ion/] [trunk/] [vhdl/] [mips_cache_stub.vhdl] - Rev 103

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Rev Log message Author Age Path
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4844d 22h /ion/trunk/vhdl/mips_cache_stub.vhdl
96 CPU rd and wr data address buses unified ja_rd 4869d 07h /ion/trunk/vhdl/mips_cache_stub.vhdl
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 4880d 03h /ion/trunk/vhdl/mips_cache_stub.vhdl
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections		 ja_rd 4888d 23h /ion/trunk/vhdl/mips_cache_stub.vhdl
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash		 ja_rd 4890d 01h /ion/trunk/vhdl/mips_cache_stub.vhdl
73 Fixed comment about write cycles in cache module ja_rd 4890d 05h /ion/trunk/vhdl/mips_cache_stub.vhdl
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles		 ja_rd 4890d 05h /ion/trunk/vhdl/mips_cache_stub.vhdl
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)		 ja_rd 4890d 18h /ion/trunk/vhdl/mips_cache_stub.vhdl
58 Cleaned up cache stub code ja_rd 4892d 18h /ion/trunk/vhdl/mips_cache_stub.vhdl
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache		 ja_rd 4893d 00h /ion/trunk/vhdl/mips_cache_stub.vhdl
43 added comments to dummy 'cache' stub ja_rd 4895d 07h /ion/trunk/vhdl/mips_cache_stub.vhdl
42 Added cache stub module, plus related test bench ja_rd 4897d 02h /ion/trunk/vhdl/mips_cache_stub.vhdl

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