URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [mips_cpu.vhdl] - Rev 46

Rev	Log message	Author	Age	Path
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	4894d 07h	/ion/trunk/vhdl/mips_cpu.vhdl
35	CPU mem_wait logic updated to work with cache	ja_rd	4898d 11h	/ion/trunk/vhdl/mips_cpu.vhdl
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4900d 08h	/ion/trunk/vhdl/mips_cpu.vhdl
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4900d 09h	/ion/trunk/vhdl/mips_cpu.vhdl
23	Unimplemented instruction are now trapped (barely tested)	ja_rd	4900d 14h	/ion/trunk/vhdl/mips_cpu.vhdl
22	FIXED killer bug in instruction decoder for beq & mfc0 Decoding was incomplete and beq was using wrong ALU input	ja_rd	4901d 11h	/ion/trunk/vhdl/mips_cpu.vhdl
12	Adapted multiplier unit from Plasma	ja_rd	4902d 00h	/ion/trunk/vhdl/mips_cpu.vhdl
8	Trap handling now works as in the MIPS specs: EPC points to victim instruction (break/syscall)	ja_rd	4903d 02h	/ion/trunk/vhdl/mips_cpu.vhdl
6	Fix: BREAK now aborts load and jump instructions properly	ja_rd	4903d 04h	/ion/trunk/vhdl/mips_cpu.vhdl
2	First commit (includes 'hello' demo)	ja_rd	4903d 14h	/ion/trunk/vhdl/mips_cpu.vhdl