OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] [mips_pkg.vhdl] - Rev 251

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
251 Extracted COP0 logic to separate module within CPU.
Preliminary step for COP0 refactor.
No change in functionality.
ja_rd 3838d 07h /ion/trunk/vhdl/mips_pkg.vhdl
225 Added utility functions for the initialization of BRAM memories. ja_rd 4411d 19h /ion/trunk/vhdl/mips_pkg.vhdl
162 Fixed stupid mistake in headers (date of project) ja_rd 4788d 10h /ion/trunk/vhdl/mips_pkg.vhdl
161 Added GPL license info to the vhdl headers
This project is becoming respectable :)
ja_rd 4788d 10h /ion/trunk/vhdl/mips_pkg.vhdl
134 Added 'unmapped access' flag to CPU core, meant for debug mostly.
Eventually this flag will trigger an interrupt.
ja_rd 4796d 12h /ion/trunk/vhdl/mips_pkg.vhdl
120 Updated main package with lots of wait states for all areas ja_rd 4854d 13h /ion/trunk/vhdl/mips_pkg.vhdl
85 BUG FIX: log2 function was wrong ja_rd 4898d 14h /ion/trunk/vhdl/mips_pkg.vhdl
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 4907d 09h /ion/trunk/vhdl/mips_pkg.vhdl
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash
ja_rd 4908d 11h /ion/trunk/vhdl/mips_pkg.vhdl
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles
ja_rd 4908d 16h /ion/trunk/vhdl/mips_pkg.vhdl
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)
ja_rd 4909d 04h /ion/trunk/vhdl/mips_pkg.vhdl
48 Temporary fix to memory decoding constants ja_rd 4911d 10h /ion/trunk/vhdl/mips_pkg.vhdl
37 functions added to package for standard address decoding ja_rd 4915d 13h /ion/trunk/vhdl/mips_pkg.vhdl
12 Adapted multiplier unit from Plasma ja_rd 4919d 03h /ion/trunk/vhdl/mips_pkg.vhdl
2 First commit (includes 'hello' demo) ja_rd 4920d 17h /ion/trunk/vhdl/mips_pkg.vhdl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.