OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl] - Rev 116

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
116 Updated demo 'top' file for DE-1 board
- Added reset button debouncing
- Added template for using different clock input
- Uses clock rate generic
ja_rd 4913d 15h /ion/trunk/vhdl
115 Updated Altera CSV file (pin location file) for DE-1 board
(Added 27MHz clock input)
ja_rd 4913d 18h /ion/trunk/vhdl
114 ADDED: 1st version of real cache ja_rd 4913d 18h /ion/trunk/vhdl
112 Updated simulation package for compatibility to new cache ja_rd 4913d 19h /ion/trunk/vhdl
103 ADDED cache control inputs (unused) to dummy cache ja_rd 4922d 10h /ion/trunk/vhdl
101 FIX: code_rd_vma asserted only after reset is done
ADDED cache control bits to CP0 status register
ADDED cache control outputs
ja_rd 4922d 10h /ion/trunk/vhdl
98 CPU rd and wr data address buses unified ja_rd 4946d 19h /ion/trunk/vhdl
96 CPU rd and wr data address buses unified ja_rd 4946d 19h /ion/trunk/vhdl
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 4957d 15h /ion/trunk/vhdl
94 Pregenerated demo 'hello' files updated ja_rd 4957d 15h /ion/trunk/vhdl
85 BUG FIX: log2 function was wrong ja_rd 4957d 16h /ion/trunk/vhdl
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script
ja_rd 4957d 16h /ion/trunk/vhdl
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong
ja_rd 4957d 16h /ion/trunk/vhdl
82 bug fix: SLTI wasn't working properly in some cases ja_rd 4959d 16h /ion/trunk/vhdl
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 4966d 11h /ion/trunk/vhdl
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections
ja_rd 4966d 11h /ion/trunk/vhdl
76 Adapted pregenerated vhdl files to latest changes ja_rd 4967d 13h /ion/trunk/vhdl
75 Added support for 8-bit-wide static memory (e.g. Flash)
Updated demo 'top' file to use the DE-1 onboard flash
ja_rd 4967d 13h /ion/trunk/vhdl
74 Fixed (harmless) error in simulation template 2 ja_rd 4967d 17h /ion/trunk/vhdl
73 Fixed comment about write cycles in cache module ja_rd 4967d 17h /ion/trunk/vhdl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.