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[/] [ion/] [trunk/] [vhdl] - Rev 74

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Rev Log message Author Age Path
74 Fixed (harmless) error in simulation template 2 ja_rd 4905d 02h /ion/trunk/vhdl
73 Fixed comment about write cycles in cache module ja_rd 4905d 03h /ion/trunk/vhdl
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles		 ja_rd 4905d 03h /ion/trunk/vhdl
68 Updated pre-generated vhdl files ja_rd 4905d 15h /ion/trunk/vhdl
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)		 ja_rd 4905d 15h /ion/trunk/vhdl
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display		 ja_rd 4905d 15h /ion/trunk/vhdl
62 CPU fixed:
fixed bug in EPC load logic relative to mem_wait stalls
parametrized reset and trap vector addresses		 ja_rd 4905d 15h /ion/trunk/vhdl
60 Forgot to upload new TB package!!
Without this, simulations don't work...		 ja_rd 4905d 15h /ion/trunk/vhdl
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file		 ja_rd 4907d 04h /ion/trunk/vhdl
58 Cleaned up cache stub code ja_rd 4907d 15h /ion/trunk/vhdl
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit		 ja_rd 4907d 17h /ion/trunk/vhdl
48 Temporary fix to memory decoding constants ja_rd 4907d 21h /ion/trunk/vhdl
47 Pre-generated simulation test benches updated ja_rd 4907d 21h /ion/trunk/vhdl
46 First version of cache: stub, 1-word cache
Stub cache tested on simulation and HW, just a stub
Adapted CPU stall logic to 1st version of cache
Adapted all other modules for compatibility with cache		 ja_rd 4907d 21h /ion/trunk/vhdl
43 added comments to dummy 'cache' stub ja_rd 4910d 05h /ion/trunk/vhdl
42 Added cache stub module, plus related test bench ja_rd 4911d 23h /ion/trunk/vhdl
40 pre-generated 'hello' demo updated ja_rd 4911d 23h /ion/trunk/vhdl
37 functions added to package for standard address decoding ja_rd 4912d 00h /ion/trunk/vhdl
36 pre-generated simulation test bench TB1 updated
for compatibility to other changes		 ja_rd 4912d 00h /ion/trunk/vhdl
35 CPU mem_wait logic updated to work with cache ja_rd 4912d 00h /ion/trunk/vhdl

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