URL https://opencores.org/ocsvn/iqcorrection/iqcorrection/trunk

Subversion Repositories iqcorrection

[/] [iqcorrection/] - Rev 44

Rev	Log message	Author	Age	Path
44	Here is an exported PDF of the workspace I used to create and test this design. Aldec Active-HDL student edition (version 7.2) was used. This PDF contains the VHDL files and two images of the waveforms. The first image highlights the gain and phase lock behavior. The second image is the first few samples. This implementation has no filter delay because the architecture is implemented with real variables instead of signed registers. This is an intermediate step along the way.	Abraxas3d	4911d 23h	/iqcorrection
43		Abraxas3d	4912d 00h	/iqcorrection
42		Abraxas3d	4912d 00h	/iqcorrection
41		Abraxas3d	4912d 00h	/iqcorrection
40		Abraxas3d	4912d 00h	/iqcorrection
39		Abraxas3d	4912d 00h	/iqcorrection
38		Abraxas3d	4912d 00h	/iqcorrection
37		Abraxas3d	4912d 00h	/iqcorrection
36		Abraxas3d	4912d 00h	/iqcorrection
35		Abraxas3d	4912d 00h	/iqcorrection
34		Abraxas3d	4912d 00h	/iqcorrection
33		Abraxas3d	4912d 00h	/iqcorrection
32		Abraxas3d	4912d 00h	/iqcorrection
31		Abraxas3d	4912d 00h	/iqcorrection
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29		Abraxas3d	4912d 00h	/iqcorrection
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27		Abraxas3d	4912d 00h	/iqcorrection
26		Abraxas3d	4912d 00h	/iqcorrection
25		Abraxas3d	4912d 00h	/iqcorrection