URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [HalfDuplexUartIf.v] - Rev 18

Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	4996d 02h	/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v
15	tpdu level tasks inverse convention	acapola	5018d 00h	/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v
11	added BSD licence header to files	acapola	5033d 03h	/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v
10	communication direction probe added	acapola	5033d 04h	/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	5041d 23h	/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	5044d 23h	/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v
3	initial draft, not functional yet	acapola	5052d 00h	/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v
2		acapola	5052d 02h	/iso7816_3_master/trunk/sources/HalfDuplexUartIf.v