URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [Iso7816_3_Master.v] - Rev 18

Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	4839d 08h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
17	yet another fix of the analyzer: ATR, and convention handling	acapola	4856d 07h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
15	tpdu level tasks inverse convention	acapola	4861d 06h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
11	added BSD licence header to files	acapola	4876d 09h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
10	communication direction probe added	acapola	4876d 10h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4885d 05h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4887d 05h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4888d 06h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
3	initial draft, not functional yet	acapola	4895d 07h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v
2		acapola	4895d 08h	/iso7816_3_master/trunk/sources/Iso7816_3_Master.v