URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [RxCore.v] - Rev 10

Rev	Log message	Author	Age	Path
10	communication direction probe added	acapola	4863d 02h	/iso7816_3_master/trunk/sources/RxCore.v
9	parity convention fixed	acapola	4868d 22h	/iso7816_3_master/trunk/sources/RxCore.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4871d 20h	/iso7816_3_master/trunk/sources/RxCore.v
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4873d 21h	/iso7816_3_master/trunk/sources/RxCore.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4874d 21h	/iso7816_3_master/trunk/sources/RxCore.v
2		acapola	4881d 23h	/iso7816_3_master/trunk/sources/RxCore.v