URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [RxCore.v] - Rev 18

Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	4828d 05h	/iso7816_3_master/trunk/sources/RxCore.v
16	just cosmetic	acapola	4849d 04h	/iso7816_3_master/trunk/sources/RxCore.v
11	added BSD licence header to files	acapola	4865d 06h	/iso7816_3_master/trunk/sources/RxCore.v
10	communication direction probe added	acapola	4865d 08h	/iso7816_3_master/trunk/sources/RxCore.v
9	parity convention fixed	acapola	4871d 04h	/iso7816_3_master/trunk/sources/RxCore.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4874d 02h	/iso7816_3_master/trunk/sources/RxCore.v
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4876d 03h	/iso7816_3_master/trunk/sources/RxCore.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4877d 03h	/iso7816_3_master/trunk/sources/RxCore.v
2		acapola	4884d 05h	/iso7816_3_master/trunk/sources/RxCore.v