URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [TxCore.v] - Rev 18

Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	5020d 23h	/iso7816_3_master/trunk/sources/TxCore.v
12	pps sequence added to test bench endOfTx added to TxCore	acapola	5057d 20h	/iso7816_3_master/trunk/sources/TxCore.v
11	added BSD licence header to files	acapola	5058d 00h	/iso7816_3_master/trunk/sources/TxCore.v
10	communication direction probe added	acapola	5058d 01h	/iso7816_3_master/trunk/sources/TxCore.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	5069d 21h	/iso7816_3_master/trunk/sources/TxCore.v
2		acapola	5076d 23h	/iso7816_3_master/trunk/sources/TxCore.v