URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources/] [Uart.v] - Rev 18

Rev	Log message	Author	Age	Path
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	4825d 21h	/iso7816_3_master/trunk/sources/Uart.v
15	tpdu level tasks inverse convention	acapola	4847d 19h	/iso7816_3_master/trunk/sources/Uart.v
12	pps sequence added to test bench endOfTx added to TxCore	acapola	4862d 18h	/iso7816_3_master/trunk/sources/Uart.v
11	added BSD licence header to files	acapola	4862d 22h	/iso7816_3_master/trunk/sources/Uart.v
10	communication direction probe added	acapola	4863d 00h	/iso7816_3_master/trunk/sources/Uart.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4871d 18h	/iso7816_3_master/trunk/sources/Uart.v
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4873d 18h	/iso7816_3_master/trunk/sources/Uart.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4874d 19h	/iso7816_3_master/trunk/sources/Uart.v
2		acapola	4881d 21h	/iso7816_3_master/trunk/sources/Uart.v