URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [sources] - Rev 19

Rev	Log message	Author	Age	Path
19	ATR analyzer fixed to handle 3b 90 97 40 20 correctly	acapola	4833d 13h	/iso7816_3_master/trunk/sources
18	A bunch of synthesis error/warning removed. Master and analyzer synthesis OK on Spartan6 FPGA	acapola	4874d 21h	/iso7816_3_master/trunk/sources
17	yet another fix of the analyzer: ATR, and convention handling	acapola	4891d 20h	/iso7816_3_master/trunk/sources
16	just cosmetic	acapola	4895d 20h	/iso7816_3_master/trunk/sources
15	tpdu level tasks inverse convention	acapola	4896d 19h	/iso7816_3_master/trunk/sources
12	pps sequence added to test bench endOfTx added to TxCore	acapola	4911d 18h	/iso7816_3_master/trunk/sources
11	added BSD licence header to files	acapola	4911d 22h	/iso7816_3_master/trunk/sources
10	communication direction probe added	acapola	4912d 00h	/iso7816_3_master/trunk/sources
9	parity convention fixed	acapola	4917d 20h	/iso7816_3_master/trunk/sources
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4920d 18h	/iso7816_3_master/trunk/sources
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4922d 19h	/iso7816_3_master/trunk/sources
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4923d 19h	/iso7816_3_master/trunk/sources
3	initial draft, not functional yet	acapola	4930d 20h	/iso7816_3_master/trunk/sources
2		acapola	4930d 21h	/iso7816_3_master/trunk/sources