URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] [tbIso7816_3_Master.v] - Rev 9

Rev	Log message	Author	Age	Path
9	parity convention fixed	acapola	4869d 09h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
8		acapola	4871d 07h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4872d 07h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
6	analyzer added to test bench, not functional yet...	acapola	4873d 07h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
4	Basic test bench completed for T=0: a card send ATR, reader send a command TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)	acapola	4875d 08h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v
3	initial draft, not functional yet	acapola	4882d 09h	/iso7816_3_master/trunk/test/tbIso7816_3_Master.v