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URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master] - Rev 20

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Rev Log message Author Age Path
20 acapola 4957d 21h /iso7816_3_master
19 ATR analyzer fixed to handle 3b 90 97 40 20 correctly acapola 4958d 11h /iso7816_3_master
18 A bunch of synthesis error/warning removed.
Master and analyzer synthesis OK on Spartan6 FPGA		 acapola 4999d 19h /iso7816_3_master
17 yet another fix of the analyzer: ATR, and convention handling acapola 5016d 18h /iso7816_3_master
16 just cosmetic acapola 5020d 18h /iso7816_3_master
15 tpdu level tasks
inverse convention		 acapola 5021d 17h /iso7816_3_master
14 Task to send strings as bytes improved acapola 5024d 16h /iso7816_3_master
13 Corrections in analyzer to handle TDi and historical bytes in ATR and PPS
todo: handle inverse convention		 acapola 5025d 20h /iso7816_3_master
12 pps sequence added to test bench
endOfTx added to TxCore		 acapola 5036d 16h /iso7816_3_master
11 added BSD licence header to files acapola 5036d 20h /iso7816_3_master
10 communication direction probe added acapola 5036d 21h /iso7816_3_master
9 parity convention fixed acapola 5042d 17h /iso7816_3_master
8 acapola 5044d 16h /iso7816_3_master
7 - rx/tx use "cyclesPerEtu" input
- "stopBit" status bit timing fixed
- analyzer: "lastByte" and "bytesCnt" functional		 acapola 5045d 16h /iso7816_3_master
6 analyzer added to test bench, not functional yet... acapola 5046d 16h /iso7816_3_master
5 draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself) acapola 5047d 16h /iso7816_3_master
4 Basic test bench completed for T=0: a card send ATR, reader send a command
TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)		 acapola 5048d 17h /iso7816_3_master
3 initial draft, not functional yet acapola 5055d 18h /iso7816_3_master
2 acapola 5055d 19h /iso7816_3_master
1 The project and the structure was created root 5056d 15h /iso7816_3_master

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