URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] [trunk/] [vhdl] - Rev 35

Rev	Log message	Author	Age	Path
35	CPM demo pin assignment file (Altera Quartus II)	ja_rd	5526d 16h	/light8080/trunk/vhdl
34	rs232 sanitized and parametrized	ja_rd	5526d 16h	/light8080/trunk/vhdl
31	New directory structure.	root	5657d 20h	/light8080/trunk/vhdl
22	Totally changed -- vhdl code generated from a template Interrupts tested from software using a simulated interrupt controller	ja_rd	5678d 02h	/trunk/vhdl
21	Totally changed -- vhdl code generated from a template	ja_rd	5678d 02h	/trunk/vhdl
20	VHDL template for test benches	ja_rd	5678d 02h	/trunk/vhdl
19	Fixed a bug (intr pulses longer than 1 clock cycle failed in some circumstances) Added an output to the core to mark the fetch cycle of all instructions Started to add timing diagrams	ja_rd	5678d 02h	/trunk/vhdl
13	Minor changes in embedded code changed (success code now stands out better visually) Comments added explaining the TB mechanincs	ja_rd	5764d 05h	/trunk/vhdl
12	Minor changes in embedded code changed (success code now stands out better visually)	ja_rd	5764d 05h	/trunk/vhdl
11	typos fixed	ja_rd	5764d 05h	/trunk/vhdl
10	minor edits, comments clarified	ja_rd	5791d 19h	/trunk/vhdl
6	microcode bug in INR M, #setacy flag missing	ja_rd	5861d 05h	/trunk/vhdl
4	light8080.vhdl comments in header corrected (they were obsolete)	ja_rd	6140d 07h	/trunk/vhdl
3	added author line and license file	ja_rd	6146d 23h	/trunk/vhdl
2	initial commit	ja_rd	6148d 09h	/trunk/vhdl