URL https://opencores.org/ocsvn/mdct/mdct/trunk

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[/] [mdct/] [trunk/] [source/] [DCT1D.vhd] - Rev 27

Rev	Log message	Author	Age	Path
27	Inserted multiple stage pipeline for final adders to improve greatly performance with expense of area.	mikel262	5562d 12h	/mdct/trunk/source/DCT1D.vhd
24	New directory structure.	root	5570d 07h	/mdct/trunk/source/DCT1D.vhd
18	Minor fixes. This release is FPGA proven.	mikel262	6597d 09h	/mdct/trunk/source/DCT1D.vhd
15	Redesigned. Fully pipelined, always ready for data design	mikel262	6619d 07h	/mdct/trunk/source/DCT1D.vhd
13	performance improved by 8%, latency reduced to 94 cycles	mikel262	6623d 06h	/mdct/trunk/source/DCT1D.vhd
10	+ moved memory allocation request to where it should be + reduced latency to 104 cycles	mikel262	6625d 07h	/mdct/trunk/source/DCT1D.vhd
7	documentation update. minor area optimization.	mikel262	6628d 05h	/mdct/trunk/source/DCT1D.vhd
4	area optimization - 100 slices less	mikel262	6629d 07h	/mdct/trunk/source/DCT1D.vhd
2	Initial import (Beta Release)	mikel262	6629d 19h	/mdct/trunk/source/DCT1D.vhd