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[/] [mdct/] [trunk] - Rev 28

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Rev Log message Author Age Path
28 updated doc mikel262 5593d 19h /mdct/trunk
27 Inserted multiple stage pipeline for final adders to improve greatly performance with expense of area. mikel262 5593d 19h /mdct/trunk
24 New directory structure. root 5601d 14h /mdct/trunk
22 project released under LGPL mikel262 5603d 19h /trunk
21 Fix for XST synthesis error and improve readibility (by Andreas Bergmann). mikel262 5603d 20h /trunk
20 Fix for XST synthesis error and improve readibility (by Andreas Bergman). mikel262 5603d 20h /trunk
18 Minor fixes. This release is FPGA proven. mikel262 6628d 16h /trunk
16 Documentation update, minor fixes mikel262 6650d 13h /trunk
15 Redesigned. Fully pipelined, always ready for data design mikel262 6650d 14h /trunk
13 performance improved by 8%, latency reduced to 94 cycles mikel262 6654d 13h /trunk
11 changed ROM memory model to synchronous mikel262 6655d 13h /trunk
10 + moved memory allocation request to where it should be
+ reduced latency to 104 cycles
mikel262 6656d 15h /trunk
8 Updated DOC mikel262 6659d 01h /trunk
7 documentation update. minor area optimization. mikel262 6659d 12h /trunk
6 minor updates mikel262 6660d 12h /trunk
4 area optimization - 100 slices less mikel262 6660d 14h /trunk
2 Initial import (Beta Release) mikel262 6661d 02h /trunk
1 Standard project directories initialized by cvs2svn. 6661d 02h /trunk

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