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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] [sim_lib/] [fpga_memory_primitives.v] - Rev 144

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109 Creating a branche for release candidate 1.0. rfajardo 4767d 23h /minsoc/branches/rc-1.0/bench/verilog/sim_lib/fpga_memory_primitives.v
27 Simulation library fpga_memory_primitives.v had an issue with its lpm_ram_dq module, which did not output its data.

The data was being output to doq instead of q, the declared output. doq was also not defined anywhere else.

Icarus Verilog did not detect this, because Verilog-2001 allows internal wires to be used without being defined. To detect this errors, one can define "`default_nettype none". After doing this, Icarus Verilog detected that error and nothing else.

doq changed to q, error corrected.		 rfajardo 5322d 04h /minsoc/branches/rc-1.0/bench/verilog/sim_lib/fpga_memory_primitives.v
17 Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.

send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)

If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.		 rfajardo 5476d 04h /minsoc/branches/rc-1.0/bench/verilog/sim_lib/fpga_memory_primitives.v
10 Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v.

With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers.

minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.		 rfajardo 5515d 03h /minsoc/branches/rc-1.0/bench/verilog/sim_lib/fpga_memory_primitives.v

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