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[/] [minsoc/] [branches/] [rc-1.0/] [prj] - Rev 113

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113 minsoc-install.sh & minsoc-configure.sh:
-aware of location of configure.sh script
configure.sh:
-does not block on patch error

spartan3e_starter_kit & spartan3e_starter_kit_eth:
-or1200_defines.v updated

prj:
-src/blackboxes/or1200_top.v adjusted to or1200_rel1
-Makefile had a typo regarding altera vhdl files		 rfajardo 4760d 18h /minsoc/branches/rc-1.0/prj
110 Fixing several minor issues with the system:
-minsoc-install splitted into installation and configuration
-minsoc-configure.sh can be used to configure a fresh checked out system
-configure script used by both minsoc-configure.sh and minsoc-install.sh to configure

-rtl/verilog: svn externals fixed
-or1200 rolled back to release-1.0

-prj/scripts:
-Makefile has been used by simulation to differentiate project definition of vhdl and verilog files
-Altera was differentiating it in script
-now there are two scripts, one for vhdl and another for verilog. The differentiation occurs in Makefile as for simulation.
-altera_3c25_board/configure scripts had to be updated, vprj and vhdprj file extensions used to differentiate Verilog and VHDL project files.

-prj/src: or1200_top.prj downdated to definition of or1200_v1		 rfajardo 4761d 10h /minsoc/branches/rc-1.0/prj
109 Creating a branche for release candidate 1.0. rfajardo 4761d 12h /minsoc/branches/rc-1.0/prj
108 Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

Icarus Verilog and Altera synthesis are working as well. Job done!		 rfajardo 4761d 15h /minsoc/trunk/prj
107 Adding setup batch script for Altera synthesis on Windows.

prj/scripts/altprj.sh has now to check if it is run from cygwin in order to re-formulate the path to windows system.

Maybe the other scripts have to be updated too. This will be checked soon.		 rfajardo 4761d 18h /minsoc/trunk/prj
104 Enabling modelsim simulation for current project definition.
vhdl and verilog projects have to be separated:
-prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS.
-Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently.
-prj/scripts/simprj.sh splitted in:
-simvhdl.sh
-simverilog.sh
(they generate the input files in the right format for simulation tools)		 rfajardo 4768d 22h /minsoc/trunk/prj
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4805d 23h /minsoc/trunk/prj
96 Some files needed for Altera synthesis javieralso 4806d 10h /minsoc/trunk/prj
95 Makefile for Altera FPGAs fixed javieralso 4807d 13h /minsoc/trunk/prj
94 Fix bug in minsoc_top.prj for Altera synthesis javieralso 4809d 22h /minsoc/trunk/prj
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4810d 00h /minsoc/trunk/prj
91 prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. rfajardo 4810d 23h /minsoc/trunk/prj
90 After minsoc_top.prj update, make regenerated src and xst files. rfajardo 4811d 15h /minsoc/trunk/prj
89 minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. rfajardo 4811d 15h /minsoc/trunk/prj
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4811d 15h /minsoc/trunk/prj
85 Central project definition under prj. Synthesis and simulation take their project files from here. rfajardo 4811d 16h /minsoc/trunk/prj

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