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[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [minsoc_bench_core.v] - Rev 10

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10 Added a file containing models for each FPGA memory instances used in or1200. The file is in bench/verilog/sim_lib/fpga_memory_primitives.v.

With it, people who change the or1200_defines.v inside of the project structure will still be able to simulate, using house-made models, not from manufacturers.

minsoc_bench.v had to be extended by the task, init_fpga_memory, to initialize the dual or two port memories instances of or1200. This has to be done based on the type of memory used, so many different instantiations based on definitions. Somehow or1200 expects all memory values to be 0 upon start, so this is necessary.		 rfajardo 5350d 20h /minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v
9 Tiny change to testbench gain:
-uart_srx is now reg for future testbench serial input to SoC.		 rfajardo 5352d 18h /minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v
8 Cosmetic changes to minsoc_bench.v:
-reset and clock initialization are included into the main initial block, it had an own block before		 rfajardo 5352d 19h /minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v
4 minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary.

jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it.

Documentation now includes:
-vpi module compilation
-gdb patch for adv_jtag_bridge
-ideas for future work on minsoc (To Do v.2)		 rfajardo 5368d 01h /minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v
2 First commit of project. Beta status:
-testbench: working
-firmware: working
-RTL: Working for: Xilinx Spartan-3A DSP Development Kit		 rfajardo 5371d 23h /minsoc/branches/verilator/bench/verilog/minsoc_bench_core.v

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