URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog] - Rev 9

Rev	Log message	Author	Age	Path
9	Tiny change to testbench gain: -uart_srx is now reg for future testbench serial input to SoC.	rfajardo	5513d 18h	/minsoc/branches/verilator/bench/verilog
8	Cosmetic changes to minsoc_bench.v: -reset and clock initialization are included into the main initial block, it had an own block before	rfajardo	5513d 18h	/minsoc/branches/verilator/bench/verilog
7	Some changes: -wb_cabs removed from minsoc_top.v and minsoc_tc_top.v -added reset polarity control to minsoc_defines.v through: -POSITIVE_RESET -NEGATIVE_RESET -minsoc_onchip_ram_top.v does not use minsoc_onchip_ram.v oe signals (output enable) anymore, which are implemented as tristate buffers. Now minsoc_onchip_ram_top.v has a generated MUX, which has an arbitrary number of inputs and 1 output. Input are the internal output of the onchip_rams, output the wb_dat_o.	rfajardo	5518d 19h	/minsoc/branches/verilator/bench/verilog
4	minsoc_bench.v had a big memory declaration to load the firmware, which was not necessary. jp-io-vpi.vpi has to be compiled for different systems so removed from the project. Documentation now explains how to do it. Documentation now includes: -vpi module compilation -gdb patch for adv_jtag_bridge -ideas for future work on minsoc (To Do v.2)	rfajardo	5529d 01h	/minsoc/branches/verilator/bench/verilog
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5532d 23h	/minsoc/branches/verilator/bench/verilog