URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [prj/] [Makefile] - Rev 104

Rev	Log message	Author	Age	Path
104	Enabling modelsim simulation for current project definition. vhdl and verilog projects have to be separated: -prj/Makefile defines VHDL_PROJECTS and VERILOG_PROJECTS, they are merged into PROJECTS. Tools which don't care about VHDL or Verilog use PROJECTS list while other tools use VERILOG_ or VHDL_PROJECTS. -Simulation uses VHDL_PROJECTS and VERILOG_PROJECTS independently. -prj/scripts/simprj.sh splitted in: -simvhdl.sh -simverilog.sh (they generate the input files in the right format for simulation tools)	rfajardo	4770d 07h	/minsoc/branches/verilator/prj/Makefile
96	Some files needed for Altera synthesis	javieralso	4807d 20h	/minsoc/branches/verilator/prj/Makefile
95	Makefile for Altera FPGAs fixed	javieralso	4808d 23h	/minsoc/branches/verilator/prj/Makefile
88	Project structure, Xilinx Makefiles and simulation working.	rfajardo	4813d 01h	/minsoc/branches/verilator/prj/Makefile
85	Central project definition under prj. Synthesis and simulation take their project files from here.	rfajardo	4813d 02h	/minsoc/branches/verilator/prj/Makefile