URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [verilator/] [rtl/] [verilog/] [minsoc_startup/] [spi_clgen.v] - Rev 139

Rev	Log message	Author	Age	Path
139	Creating a verilator branche.	rfajardo	4779d 10h	/minsoc/branches/verilator/rtl/verilog/minsoc_startup/spi_clgen.v
109	Creating a branche for release candidate 1.0.	rfajardo	4806d 00h	/minsoc/branches/verilator/rtl/verilog/minsoc_startup/spi_clgen.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5574d 08h	/minsoc/branches/verilator/rtl/verilog/minsoc_startup/spi_clgen.v