| Rev |
Log message |
Author |
Age |
Path |
| 93 |
Support for Altera synthesis. It needs some tune, but it works fine |
javieralso |
4657d 03h |
/minsoc/branches/verilator |
| 92 |
backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. |
rfajardo |
4658d 01h |
/minsoc/branches/verilator |
| 91 |
prj/scripts/: Changing scripts not to include multiple timescale.v files from different listed directories in the project definition file. Instead, now the internal loop which look for the file in different directories is broken when the first file is found. |
rfajardo |
4658d 02h |
/minsoc/branches/verilator |
| 90 |
After minsoc_top.prj update, make regenerated src and xst files. |
rfajardo |
4658d 17h |
/minsoc/branches/verilator |
| 89 |
minsoc_top.prj was splited into minsoc_top and minsoc_bench. minsoc_top still had directory entries of bench, they are gone now. |
rfajardo |
4658d 17h |
/minsoc/branches/verilator |
| 88 |
Project structure, Xilinx Makefiles and simulation working. |
rfajardo |
4658d 17h |
/minsoc/branches/verilator |
| 87 |
Synchronizing scripts to behave exactly the same. |
rfajardo |
4658d 19h |
/minsoc/branches/verilator |
| 86 |
Updating configure script messages. |
rfajardo |
4658d 19h |
/minsoc/branches/verilator |
| 85 |
Central project definition under prj. Synthesis and simulation take their project files from here. |
rfajardo |
4658d 19h |
/minsoc/branches/verilator |
| 84 |
syn/blackboxes/eth_top.v:
-module is now called ethmac instead of eth_top
-eth_defines.v is now called ethmac_defines.v |
rfajardo |
4659d 19h |
/minsoc/branches/verilator |
| 83 |
minsoc-install.sh: bzip2 program was being used, but its existance on target system was not being verified. It is now. |
rfajardo |
4671d 01h |
/minsoc/branches/verilator |
| 82 |
minsoc-install.sh: problems with copying the GNU Toolchain from download to tools. We uncompress the GNU Toolchain now once again to tools during the installation part. |
rfajardo |
4674d 00h |
/minsoc/branches/verilator |
| 81 |
Installation script complete, nice text feedback, output logs and better execution order. |
rfajardo |
4674d 11h |
/minsoc/branches/verilator |
| 80 |
Establishing a better Makefile system for firmwares. |
rfajardo |
4676d 23h |
/minsoc/branches/verilator |
| 79 |
minsoc-install.sh: rpath corrected.
required-cygwin-tools: updated |
rfajardo |
4677d 16h |
/minsoc/branches/verilator |
| 78 |
minsoc-install.sh: Advanced JTAG bridge compilation needs to know where the dynamic libraries are on runtime. Patching (sed) the Makefile to compile it with the rpath to the libraries (libusb/libftdi). |
rfajardo |
4677d 16h |
/minsoc/branches/verilator |
| 77 |
New tool requirements for installing Icarus Verilog. |
rfajardo |
4677d 17h |
/minsoc/branches/verilator |
| 76 |
Including a script allowing the installation of MinSoC and all its required tools.
It should be working for all Linuxes and Cygwin. |
rfajardo |
4677d 17h |
/minsoc/branches/verilator |
| 75 |
Adapting minsoc_top.v and minsoc_verilog_files.txt to new names for top modules and define file of ethmac ip core. |
rfajardo |
4684d 17h |
/minsoc/branches/verilator |
| 74 |
or1200.h includes a CLABLE macro which uses __USER_LABEL_PREFIX__(from compiler defined macro) to find out if we need the underscore as prefix to reference C functions (its assembly labels) or not.
except.S and reset.S use CLABLE to call externally defined C functions.
This should avoid problems compiling firmware with old or new toolchain.
support/common.mk updated, reset-nocache.o and reset-icdc.o are dependent on or1200.h |
rfajardo |
4777d 15h |
/minsoc/branches/verilator |
