OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [backend] - Rev 174

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
174 Rok Krajnc port of the Altera DE1 board with a Cyclone II. Thanks a lot! rfajardo 4239d 06h /minsoc/trunk/backend
173 Jay Aurabind's contribution of a port to the Nexys 3 board from Digilent. Thanks!! rfajardo 4239d 06h /minsoc/trunk/backend
168 Installation script has an option for advanced or resumed installation.
Advanced mode:
the script only downloads and installs the required tools. Dependency libraries and tools are checked during individual tool compilation. Furthermore, the install directory is not added to the system PATH. You have to do it yourself. Libusb, libftdi and Icarus Verilog are supposed to be installed by the user.
Resumed mode:
the script checks if the dependency libraries and tools are installed before doing anything. It also adds the installation directory to the system PATH variable for bash shells on HOME/.bashrc. Libusb, libftdi and Icarus Verilog are automatically installed for you.

Non standard configuration scripts that require or1200_defines.v to be tweaked will ask before doing so and backup the correspondent files.		 rfajardo 4540d 08h /minsoc/trunk/backend
165 Board contribution: nexys2_1200 (Thanks to Johan Granath)

spartan3e_starter_kit_eth/minsoc_bench_defines.v: deprecated definition updated		 rfajardo 4605d 11h /minsoc/trunk/backend
159 Updated constraint file for de2_115 board. (Richard Hasha) rfajardo 4695d 09h /minsoc/trunk/backend
158 Adding de2_115_board port, thanks to Richard Hasha.

Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
-Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

prj/srcs extended to include jsp and interconnec_defines.v.

spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.		 rfajardo 4697d 01h /minsoc/trunk/backend
149 Merging differences of release candidate 1.0 revision 140:148 with trunk. rfajardo 4735d 11h /minsoc/trunk/backend
144 Updating configure scripts. Calling make into the right directories now. rfajardo 4741d 10h /minsoc/trunk/backend
142 Updating configure.sh:
1) we don't patch the trunk version.
2) it is better to re-compile the firmwares on reconfiguration. So compiling firmwares went to configure scripts instead.

backend/xxx/configure: compiling firmwares here now.		 rfajardo 4741d 10h /minsoc/trunk/backend
141 Merging with rc-1.0 revision 140. I doubt rc-1.0 will still change much in the last days. rfajardo 4741d 10h /minsoc/trunk/backend
105 Updating configure scripts to copy Windows synthesis launch script setup.bat from either minsoc/syn/altera or minsoc/syn/xilinx to minsoc/syn. rfajardo 4768d 11h /minsoc/trunk/backend
99 backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails. rfajardo 4812d 11h /minsoc/trunk/backend
97 As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board. rfajardo 4812d 12h /minsoc/trunk/backend
96 Some files needed for Altera synthesis javieralso 4812d 22h /minsoc/trunk/backend
95 Makefile for Altera FPGAs fixed javieralso 4814d 02h /minsoc/trunk/backend
93 Support for Altera synthesis. It needs some tune, but it works fine javieralso 4816d 13h /minsoc/trunk/backend
92 backend/spartan3e_starter_kit*: or1200_defines.v file was outdated and hindering synthesis. Probably it would be best if we used a patching system here. But for now, I copied the new files and made the necessary changes to fit the system into the target boards. rfajardo 4817d 11h /minsoc/trunk/backend
88 Project structure, Xilinx Makefiles and simulation working. rfajardo 4818d 04h /minsoc/trunk/backend
87 Synchronizing scripts to behave exactly the same. rfajardo 4818d 05h /minsoc/trunk/backend
86 Updating configure script messages. rfajardo 4818d 05h /minsoc/trunk/backend

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.