URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

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[/] [minsoc/] [trunk/] [bench/] [verilog/] [minsoc_memory_model.v] - Rev 71

Rev	Log message	Author	Age	Path
71	Modelsim whines about missing timescales: -minsoc_bench.v, minsoc_memory_model.v and dbg_comm_vpi.v updated to include timescale.v modelsim simulation working under Windows. Modelsim PE Student Edition 10.0a Simulation<->adv_jtag_bridge<->gdb communication not working perfectly. I believe VPI module has to be recompiled, used pre-compiled one for now.	rfajardo	4926d 13h	/minsoc/trunk/bench/verilog/minsoc_memory_model.v
60	Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation. minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition.	rfajardo	4938d 01h	/minsoc/trunk/bench/verilog/minsoc_memory_model.v
2	First commit of project. Beta status: -testbench: working -firmware: working -RTL: Working for: Xilinx Spartan-3A DSP Development Kit	rfajardo	5525d 12h	/minsoc/trunk/bench/verilog/minsoc_memory_model.v