URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Rev 129

Rev	Log message	Author	Age	Path
129	Added reset_in to sensitivity list	rhoads	7221d 11h	/mlite/trunk/vhdl/mem_ctrl.vhd
128	Reset all registers, constants now upper case.	rhoads	7339d 22h	/mlite/trunk/vhdl/mem_ctrl.vhd
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7539d 12h	/mlite/trunk/vhdl/mem_ctrl.vhd
95	register mem_write and mem_byte_sel for speed calculations	rhoads	8062d 16h	/mlite/trunk/vhdl/mem_ctrl.vhd
89	Use address_reg instead of address_data to break timing slow down	rhoads	8064d 09h	/mlite/trunk/vhdl/mem_ctrl.vhd
72	accurate_timing, cleanup, pipeline	rhoads	8072d 11h	/mlite/trunk/vhdl/mem_ctrl.vhd
56	Altera, added byte_sel_reg for tigher timing and avoid possible glitches	rhoads	8080d 16h	/mlite/trunk/vhdl/mem_ctrl.vhd
49	Fix pause while writting	rhoads	8091d 11h	/mlite/trunk/vhdl/mem_ctrl.vhd
47	Altera	rhoads	8098d 12h	/mlite/trunk/vhdl/mem_ctrl.vhd
43	Renamed M-lite to Plasma	rhoads	8178d 12h	/mlite/trunk/vhdl/mem_ctrl.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8210d 17h	/mlite/trunk/vhdl/mem_ctrl.vhd
8	Preparing to use dual-port memory for registers.	rhoads	8247d 12h	/mlite/trunk/vhdl/mem_ctrl.vhd
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8252d 18h	/mlite/trunk/vhdl/mem_ctrl.vhd
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8256d 17h	/mlite/trunk/vhdl/mem_ctrl.vhd
2	MIPS-lite CPU core	rhoads	8475d 17h	/mlite/trunk/vhdl/mem_ctrl.vhd