URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [mem_ctrl.vhd] - Rev 95

Rev	Log message	Author	Age	Path
95	register mem_write and mem_byte_sel for speed calculations	rhoads	8029d 09h	/mlite/trunk/vhdl/mem_ctrl.vhd
89	Use address_reg instead of address_data to break timing slow down	rhoads	8031d 03h	/mlite/trunk/vhdl/mem_ctrl.vhd
72	accurate_timing, cleanup, pipeline	rhoads	8039d 04h	/mlite/trunk/vhdl/mem_ctrl.vhd
56	Altera, added byte_sel_reg for tigher timing and avoid possible glitches	rhoads	8047d 10h	/mlite/trunk/vhdl/mem_ctrl.vhd
49	Fix pause while writting	rhoads	8058d 05h	/mlite/trunk/vhdl/mem_ctrl.vhd
47	Altera	rhoads	8065d 06h	/mlite/trunk/vhdl/mem_ctrl.vhd
43	Renamed M-lite to Plasma	rhoads	8145d 06h	/mlite/trunk/vhdl/mem_ctrl.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8177d 11h	/mlite/trunk/vhdl/mem_ctrl.vhd
8	Preparing to use dual-port memory for registers.	rhoads	8214d 05h	/mlite/trunk/vhdl/mem_ctrl.vhd
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8219d 12h	/mlite/trunk/vhdl/mem_ctrl.vhd
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8223d 10h	/mlite/trunk/vhdl/mem_ctrl.vhd
2	MIPS-lite CPU core	rhoads	8442d 11h	/mlite/trunk/vhdl/mem_ctrl.vhd